1. Field of the Invention
The present invention relates to oscillators and electronic devices, and more particularly, to an oscillator that includes a crystal oscillator used for a PLL circuit in a portable telephone, and other suitable devices, and that provides a reference frequency and to an electronic device including the oscillator.
2. Description of the Related Art
FIG. 10 is a circuit diagram of a conventional oscillator. Referring to FIG. 10, an oscillator 1 includes a transistor Q1, which defines an active element for buffer amplification (hereinafter referred to as a “buffer-amplifying active element”), a transistor Q2, which defines an active element for oscillation (hereinafter referred to as an “oscillating active element”), a crystal oscillator X1, resistors R1 to R5, and capacitors C1 to C5.
In this conventional oscillator, a power-supply terminal +Vcc, to which a positive power-supply voltage is applied, is connected to ground via the capacitor C1 and is also connected to the collector of the transistor Q1 via the resistor R1, which defines a load impedance. The collector of the transistor Q1 is connected to an output terminal Po via the capacitor C2, and the emitter thereof is connected to the collector of the transistor Q2. The emitter of the transistor Q2 is connected to ground via the resistor R2. The power-supply terminal +Vcc is also connected to ground via a sequence of the resistors R3, R4, and R5. The node of the resistors R3 and R4 is connected to the base of the transistor Q1 and is also connected to ground via the capacitor C3. The node of the resistors R4 and R5 is connected to the base of the transistor Q2 and is also connected to ground via the crystal oscillator X1. Further, the capacitor C4 is connected between the base and the emitter of the transistor Q2, and the capacitor C5 is connected in parallel with the resistor R2.
In the oscillator 1 having the configuration described above, an oscillation circuit, which is defined by the transistor Q2 and the crystal oscillator X1 is a common-collector Colpitts circuit, but is a modified Colpitts circuit since the collector of the transistor Q2 is connected to the emitter of the transistor Q1 rather than being connected to ground.
In this modified Colpitts circuit, a capacitor that is provided in the loop between the base and emitter of a transistor in a typical Colpitts circuit is the capacitor C4. A portion corresponding to an inductor that is provided in the loop between the base and the collector is a series-connected portion including the crystal oscillator X1, the capacitor C3, which is connected to the crystal oscillator X1 via ground, and the base and emitter of the transistor Q1. A portion corresponding to a capacitor provided in the loop between the emitter and the collector is a series-connected portion including the capacitor C5, the capacitor C3, which is connected to the capacitor C5 via ground, and the base and emitter of the transistor Q1.
The transistor Q1 provides a common-base buffer-amplifying circuit, in which the base thereof is connected to ground via the capacitor C3 so as to ground the base at higher frequencies. The transistor Q1 receives, at the emitter thereof, an oscillation signal output from the collector of the transistor Q2 in the oscillation circuit, and amplifies the oscillation signal and outputs it from the collector of the transistor Q1 to the output terminal Po via the capacitor C2, which eliminates direct current. Thus, the node of the resistor R1 and the transistor Q1 defines a signal outputting point.
The main electrical current in the oscillator 1 flows through the resistor R1, a first path between the collector and the emitter of the transistor Q1, the first path being a main current path of the transistor Q1, a second path between the collector and the emitter of the transistor Q2, the second path being a main current path of the transistor Q2, and the resistor R2. In other words, the transistors Q1 and Q2 are connected in series on paths through which the main current flows between the power-supply terminal +Vcc and ground.
The resistors R3, R4, and R5 are bias resistors for introducing base current to the two transistors Q1 and Q2. In the oscillator 1, since the oscillation circuit is a modified Colpitts circuit, it is not necessary to provide a capacitor for coupling between the transistors Q1 and Q2.
FIG. 11 shows voltage waveforms in individual portions of the transistors Q1 and Q2 in the oscillator 1. Of the illustrated voltages, a voltage at the collector of the transistor Q1 is an output voltage and is thus output via the capacitor C2, which eliminates direct current. As shown in FIG. 11, the slope of the waveform of the collector voltage of the transistor Q1 is gentle in the rising portion and is steep in the falling portion.
The reason for this waveform will now be described. First, the oscillation circuit, which includes the transistor Q2, oscillates using an oscillator loop that includes the crystal oscillator X1. During oscillation, the waveform of the base voltage of the transistor Q2 is a substantially sinusoidal wave due to a filtering effect of the crystal oscillator X1.
When the transistor Q2 is in the OFF state, the capacitor C5 is not charged because no current is flowing through the resistor R2. In this case, an increased base voltage of the transistor Q2 causes an increase in a voltage across the emitter and the base to turn the transistor Q2 on, and current flows between the collector and the emitter and then flows through the resistor R2 to thereby cause the emitter voltage to increase. The current, however, is first utilized for charging the capacitor C5, and thus the emitter voltage does not increase immediately. During this period, since the base voltage has a tendency to increase, the rate of increase in voltage across the base and the emitter increases, such that the transistor Q2 is rapidly turned on and the collector voltage rapidly drops. This turns off the transistor Q1 rapidly, and thus, current flows rapidly between the collector and the emitter thereof. As a result, the collector voltage (output voltage) of the transistor Q1 decreases rapidly. Thus, the waveform of the collector voltage is steep.
When the charging of the capacitor C5 ends, the current flows through the resistor R2, such that the emitter voltage of the transistor Q2 increases according to the base voltage and then decreases after reaching a maximum.
When the voltage across the base and the emitter is reduced due to a decrease in the base voltage, the transistor Q2 has a tendency to turn off, however, since the emitter voltage is reduced concurrently, the voltage across the base and the emitter slowly decreases and the transistor Q2 is turned off slowly. During this period, since the current continues to flow between the collector and the emitter of the transistor Q2 while it is decreasing, the collector voltage of the transistor Q2 increases slowly. Thus, the transistor Q1 is also turned off slowly. As a result, the collector voltage (output voltage) of the transistor Q1 also increases slowly. Thus, the slope of the waveform of the collector voltage is gentle.
Subsequently, this operation returns to the first state and the above-described cycle is repeated.
In this manner, the oscillator 1 provides an output signal that has a waveform that is gentle in the rising portion and is steep in the falling portion.
Meanwhile, in a PLL circuit using such an oscillator 1 as a reference signal source, the frequency of an output oscillation signal is stabilized such that a signal output from the oscillator 1 is frequency-divided more than once, the phase thereof is compared with the phase of a signal output from a voltage controlled oscillator having a frequency that has equivalently been pre-divided to be substantially the same, and the result is fed back to the voltage controlled oscillator.
When the signal output from the oscillator 1 is frequency-divided, a logic element (digital element) is provided at a stage prior to a frequency divider, in order to pre-shape the waveform of a signal input to the frequency divider into a rectangular waveform. Examples of the logic element includes an inverter (which herein means an inverting circuit of a logic element) and a buffer (which herein means a non-inverting circuit of a logic element) having a predetermined threshold.
A signal resulting from the waveform shaping is a rectangular waveform having a high level when the signal output from the oscillator 1 is at a level higher than the threshold of the buffer, and also having a low level when the signal output from the oscillator 1 is at a level lower than the threshold level of the buffer. When an inverter is used to shape the waveform, the high and low levels are inverted. The frequency divider in the PLL circuit performs frequency division using the rising or falling portion of a digital signal resulting from the waveform shaping as a trigger.
Further, since the frequency divider is defined by a combination of logic elements including an RS flip flop, it is also possible to perform waveform shaping concurrently with the frequency division at a first stage in the frequency divider by inputting the signal output from the oscillator 1 directly to the frequency divider.
Meanwhile, the level of the signal output from the oscillator 1 varies depending upon, for example, a change in power-supply voltage and/or ambient temperature. Further, the output achieves a high or low level depending on the relationship between a signal input to a logic element and a threshold. Thus, when a signal output from the oscillator 1 changes, as shown in part (a) of FIG. 12, due to a variation in the level of the signal, the timings of the rising or falling of a signal output from the logic element deviates as shown in part (b) of FIG. 12. As shown in FIG. 12, the deviation in timings increases as the absolute value of the gradient of the waveform of the rising portion or the falling portion of an input signal decreases. As shown in FIG. 12, with the oscillator 1, a large variation is generated in the timing of the rising portion of an output from the logic element. Thus, when the level of an oscillation signal varies with time, a fluctuation is generated in the timing of rising of a signal output from the logic element. In this case, when the absolute value of the gradient of a waveform increases, such as the waveform of the falling portion of the oscillation signal, the fluctuation in the timing decreases.
When a signal having a large timing fluctuation in the rising portion is frequency-divided, dividing the frequency thereof using the large fluctuation side as a trigger results in a large fluctuation in the resulting signal at timings of both of the rising and falling portions. This means that a fluctuation in a signal that defines a reference for the PLL circuit is large. Consequently, jitter (in an oscillation signal output from the PLL circuit), which is a fluctuation in a signal output from the voltage controlled oscillator itself increases.
Accordingly, in order to reduce jitter in an oscillation signal output from the PLL circuit, a frequency divider must be triggered so as to correspond to a portion where the absolute value of the gradient of the waveform of a signal output from an oscillator is increased.
In a typical PLL circuit, however, a frequency divider is commonly triggered in the rising portion of an input signal. Thus, when an oscillator, such as an oscillator 1, is used as a reference signal source, jitter in an oscillation signal output from the PLL circuit still increases.